NMOS Transistor PyCell with Stretch Handles

PyCell Description:

This PyCell creates a NMOS transistor with stretch handles to speed manual layout. Users may specify interdigitation, gate contact options, source and drain wiring options, and guard rings. Additional parameters are available for modifying contact-to-gate spacing and contact alignment on diffusion and gates. This PyCell automatically creates all user-specified connectivity for source and drain. The connectivity, spacing and contacts conform to the design rules for the process in use.

This PyCell also supports stretch handles in OpenAccess layout editors including Cadence® Virtuoso® and Silicon Navigator® RDE®. Click here to view an interoperability matrix showing what tools support different PyCell features.

PyCell Plot:

PyCell Parameters:

Results of Different Parameter Values:

Top & Bottom Gate Contacts
with Source & Drain Connections:		 Top Gate Contact Only with
Source Connections Only:

Process Technology:

The PyCell layouts above were generated for a generic 130nm process. This same PyCell source code has been tested to create design rule correct layout for both minimum spacing rules and recommended rules for foundry 65nm and 90nm processes, and for minimum spacing rules at 130nm, 180nm and 250nm.

Source Code:

PyCell name: Nmos3
Source name: Mosfet3.py
The complete source code for the PyCell on this page is contained in the IPL Library. A single PyCell source code file generates four library cells for MOSFETs, including NMOS and PMOS versions, and normal or high-voltage options. This PyCell includes stretch handles; another PyCell (Mosfet2.py) includes both stretch handles and automatic abutment. To download:
  1. Click here for the Ciranova downloads page. The IPL Library is on a link at the top of the page. A quick registration is required.
  2. Click here to learn more about the IPL Library
  3. Click here to see the IPL PyCell Gallery, with many more sample PyCell layouts.