PMOS Transistor PyCell with Row Stacking

PyCell Description:

This PyCell creates a PMOS transistor with many options for automated and manual layout. Users may specify the number of rows, interdigitation, dummies and guard rings. Additional parameters are available for modifying contact-to-gate spacing and contact coverage over diffusion. This PyCell automatically creates all user-specified connectivity for between fingers and rows.

The object-oriented architecture of the Ciranova Layout API handles the complex wiring requirements of multiple fingers and rows. Each finger is treated as an object that is connected by passing a numeric sequence as a method to do the actual wiring.

The connectivity, spacing and contacts conform to the design rules for the process in use.

PyCell Plot:

PyCell Parameters:

Results of Different Parameter Values:

Two Rows with Guard Ring: One Row with Dummies:

Process Technology:

The PyCell layouts above were generated for a generic 130nm process. This same PyCell source code has been tested to create design rule correct layout for both minimum spacing rules and recommended rules for foundry 65nm and 90nm processes, and for minimum spacing rules at 130nm, 180nm and 250nm.

Source Code:

PyCell name: Pmos1
Source name: Mosfet1.py
The complete source code for the PyCell on this page is contained in the IPL Library. A single PyCell source code file generates four library cells for MOSFETs, including NMOS and PMOS versions, and normal or high-voltage options. To download:
  1. Click here for the Ciranova downloads page. The IPL Library is on a link at the top of the page. A quick registration is required.
  2. Click here to learn more about the IPL Library
  3. Click here to see the IPL PyCell Gallery, with many more sample PyCell layouts.