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Ciranova Helix
Automated Production-Quality Analog Layout
- Automatically creates production-quality analog placement
- Dramatically shortens time to market for analog designs
- Enables process-portable analog IP
- Improves area efficiency at 65nm and below
Ciranova Helix is the industry's first automated physical design solution that delivers production-quality layout results on analog/mixed-signal IC designs such as PLL's, SerDes, A/D's and Phy's. It optimizes circuit and device layout simultaneously, delivering design-rule-correct layout comparable in quality to that produced by an experienced layout designer. Ciranova Helix also separates design IP from process rules, facilitating analog IP migration between processes. And it automatically optimizes for arbitrarily complex design rules, delivering tight, compact layouts even at 45nm and below.
Ciranova Helix is simple enough that both circuit and layout designers can use it: circuit designers to quickly prototype and explore different physical strategies for their designs, and layout designers to dramatically improve their productivity on production layouts. Ciranova Helix brings sophisticated physical design automation to the custom world in a fast, easy to use package.
On the left, the Ciranova Helix GUI uses a point and click interface to enter high-level constraints. On the right are three compact, design-rule-correct layouts created simultaneously by Ciranova Helix in minutes.
Ciranova Helix: Massive Productivity Improvement for Analog Layout
When layout iterations can be completed in minutes or hours, the entire physical design cycle can be reduced to a few days. This enables designers to:
- Start layout sooner and finish faster
- Explore multiple floorplan alternatives to find the best die size
- Perform what-if analysis
- Extract parasitics earlier in the design cycle
Ciranova Helix compresses the entire analog layout cycle, enabling designers to complete more designs, more quickly.
Enabling Process-Portable Analog IP
By separating Design IP (netlist and constraints) from process data, Ciranova Helix enables users to create process-portable analog IP. Ciranova’s RuleWise technology handles design rule requirements automatically, so your the Design IP can be reused to quickly reproduce layout on different processes or variations.
Integrates with Your Design Flow
OpenAccess: Ciranova Helix integrates cleanly with popular OpenAccess-compliant design flows using products such as Cadence Virtuoso 6.x, Springsoft Laker, Magma Titan, Mentor Calibre and Synopsys Hercules. Helix creates a fully editable OpenAccess database that can be utilized by any OpenAccess tool. The output of Ciranova Helix has been tested with a wide variety of OpenAccess products from many different EDA suppliers.
PCells: Ciranova Helix works with both Ciranova PyCells and Cadence® SKILL® PCells, in any combination. Ciranova Helix is able to take full advantage of advanced features built into PyCell libraries, including complex interdigitation, row stacking and automatic abutment. To see a gallery of PyCells with these productivity features and more, click here.
Availabilty
Ciranova Helix is available now on Linux, Solaris and Microsoft Windows. Please contact Ciranova for more details.
Learn More about Ciranova Helix
- Ciranova Helix in Detail
- Point and Click Control of Your Layout
- Helix Performance
- RuleWise Technology