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Ciranova Helix
Agile Layout for RF, Analog & Mixed-Signal IC Design
Ciranova Helix is the first layout automation solution to enable Agile Layout, a dramatic improvement over traditional, manual layout techniques. Using Agile Layout, IC design teams are able to start layout sooner, refine the circuit based on feedback from layout, and finish layout faster.
Because traditional layout takes so long and is so hard to change, layout designers seldom start before the circuit design is nearly complete. This means that circuit designers must wait weeks or months after their circuit is complete to learn whether the layout will meet performance and area targets.
Using an Agile layout flow, design teams can start layout early, as soon as the first blocks of a design have been completed. Helix produces initial layout results very quickly, so circuit designers can get early feedback on performance, parasitics and area. Layout designers have time to refine their designs and test alternatives, often resulting in smaller, higher-performance layouts. With Agile Layout, layout is usually finished soon after circuit designers finish their last blocks.
Ciranova Helix: Device-Level Placement for Custom IC Design
- Perform fast, accurate device-level floorplanning and high-quality placement
- Slash analog/mixed-signal layout time and get early access to layout parasitics
- Port analog IP across technologies
- Automatically optimizes to complex design rules at 28nm and below
- Easy to use by circuit and layout designers
- Supports both iPDKs and Cadence Skill PDKs
Ciranova Helix is a device-level automated placement solution for RF, analog, and mixed-signal IC designs such as PLLs, SerDes, ADCs and PHYs. A designer working with Helix can produce very high quality, design-rule-correct layout in a small fraction of the time needed using conventional methods, especially at 28nm and below.
the analog/mixed-signal layout cycle
Ciranova Helix is fully hierarchical and offers capacity in the tens of thousands of transistors, enabling it to optimize floorplanning and placement for entire custom IC blocks or IP at once. Its output is a standard OpenAccess database that can be read and edited in any OpenAccess layout editor, such as Cadence Virtuoso 6.x, Synopsys Galaxy Custom Designer, Springsoft Laker, or Magma Titan.
Automate Custom Layout at 40nm and Below
Starting with just a netlist, Ciranova Helix can automatically generate the initial constraint set for a circuit. Within hours, Helix can produce initial layout suitable for estimating parasitics and area, even if the circuit design is only partially complete.
for the charge pump and clock generator blocks
Using this initial layout, designers can floorplan their design top-down, constraining size, pin locations and block relationships. Or they can start at the device level, building the layout bottom-up. In either case, the automated initial layout dramatically compresses the time needed to get the initial layout results.
Explore Layout Options & Refine Circuit Design
When layout is done manually, designers seldom get to see more than one floorplan of their circuit because of time constraints. Using Helix in an Agile Layout flow, designers are able to explore multiple layouts, make tradeoffs, and reduce unnecessary margins.
Helix creates the full range of minimum-spacing layout alternatives that meet constraints and are DRC correct. By creating these layouts quickly, Helix enables design teams to iterate the circuit and layout together, maximizing performance and area utilization.
With a capacity of tens of thousands of devices, Helix can handle entire analog and mixed signal function blocks without requiring designers to create dozens of small layout partitions. Using Helix to quickly explore multiple footprints, designers can typically save 5%-15% or more die size, compared with manual layout on a tight schedule.
Accelerate Your Existing OpenAccess Layout Flow
Helix fits easily into OpenAccess-compatible design flows. Inputs are a SPICE netlist and PDK. Helix can also read an OpenAccess schematic to enable schematic-based constraint creation and cross probing between schematic, constraint and layout views.
Helix output is a standard OpenAccess database that can be edited in any OpenAccess layout editor, such as Cadence Virtuoso 6.x, Synopsys Galaxy Custom Designer, Springsoft Laker, or Magma Titan. Helix works with both Ciranova PyCells and Cadence SKILL® PCells, in any combination. All Helix layouts are design rule correct.
Enabling Process-Portable Analog IP
By separating Design IP (netlist and constraints) from process data, Ciranova Helix helps users to create process-portable analog IP. Ciranova's RuleWise technology handles design rule requirements automatically. As long as you use a process-portable PCell library and your circuit topology remains the same, your Design IP can be reused to quickly create new layout on different processes or variations.
Learn More about Ciranova Helix