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Ciranova Helix
Device-Level Placement for RF, Analog & Mixed-Signal IC Design
- Slash analog/mixed-signal layout time
- Perform fast, accurate device-level floorplanning
- Get early access to layout parasitics
- Port analog IP across technologies
Ciranova Helix is a device-level placement solution for RF, analog, and mixed-signal IC designs such as PLLs, SerDes, ADCs and PHYs. A designer working with Helix can produce very high quality, design-rule-correct layout in a fraction of the time needed using conventional methods, especially at silicon geometries below 90nm. Ciranova Helix's high capacity, in the tens of thousands of transistors, makes it useful for accurately exploring different floorplans for a given circuit. An integrated trial router makes it straightforward to generate extractable layouts for parasitic resimulation. When used with the appropriate PyCell library, Helix dramatically simplifies the porting of analog IP from one technology to another.
Helix fits easily into OpenAccess-compatible design flows. Its output is a standard OpenAccess database that can be read and edited in any OpenAccess layout editor, such as Cadence Virtuoso 6.x, Synopsys Galaxy Custom Designer, Springsoft Laker, or Magma Titan.
Ciranova Helix is simple to use by both circuit and layout designers: circuit designers can quickly prototype and explore different physical strategies for their designs, and layout designers can dramatically improve their productivity on production layouts. Ciranova Helix brings sophisticated physical design automation to the custom IC world in a fast, easy to use package.
Dramatic Productivity Improvement for Analog Layout
Ciranova Helix dramatically compresses the time needed for custom IC physical design, especially when complex design rules are required at advanced silicon geometries. Helix creates high-quality, DRC-correct placement iterations in minutes or hours, reducing the entire physical design cycle to days. This enables designers not only to save layout time and expense, but also to start exploring layouts well before the circuit design is complete.
The result is better designs, sooner.
Support for Your Floorplanning Process
Helix generates multiple placements of circuits up to tens of thousands of transistors. This lets you quickly generate many different physical footprints for your design, at different pitches and aspect ratios, each using a full DRC-correct device-level placement. You can quickly try different pinouts or other high-level guidance, and see what the resulting layout will really look like.
Most analog engineers never get to see more than one floorplan of their circuit. With Helix, you can explore many different floorplans and choose the layout strategy that best suits your design.
Trial-Routing for Early Layout Parasitics
The optional trial router, available in late 2009, works with Helix placement to produce first-pass interconnect for the design. The trial-routed design is a standard OpenAccess database that you can run through your normal parasitic extraction and resimulation flow to assess the performance of the design, and compare to prelayout simulations. With Helix, the time needed from schematic to an extractable layout is so short that you can start seeing layout parasitics within days, and sometimes within hours, of starting layout. Often this can be done even while the circuit design is still in progress.
The trial routes follow your process design rules, but do not contain the production vias, shielding, tapering and other characteristics of the final tapeout route. In addition to supporting parasitic extraction, the trial route helps designers assess the overall routability of the design and can serve as preliminary guidance to the production routing.
Enabling Process-Portable Analog IP
By separating Design IP (netlist and constraints) from process data, Ciranova Helix helps users to create process-portable analog IP. Ciranova's RuleWise technology handles design rule requirements automatically. As long as you use a process-portable PyCell library and your circuit topology remains the same, your Design IP can be reused to quickly create new layout on different processes or variations.
Integrates with Your Design Flow
OpenAccess: Ciranova Helix integrates cleanly with popular OpenAccess-compliant design flows using products such as Cadence Virtuoso 6.x, Synopsys Galaxy Custom Designer, Springsoft Laker, and Magma Titan. Helix creates a fully editable OpenAccess database that can be utilized by any OpenAccess tool.
PCells: Ciranova Helix works with both Ciranova PyCells and Cadence SKILL® PCells, in any combination. Ciranova Helix is able to take full advantage of advanced features built into PyCell libraries, including complex interdigitation, row stacking and automatic abutment. To see a gallery of PyCells with these productivity features and more, click here.
(shown: Synopsys Galaxy Custom Designer)
Availabilty
Ciranova Helix is available now on Linux, Solaris and Microsoft Windows. Please contact Ciranova for more details.
Learn More about Ciranova Helix
- Online Helix Demos
- High Quality Placement Results
- Point and Click Control of Your Layout
- RuleWise Technology