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High Quality Placement Results
First and foremost, an automated solution must create placement with quality acceptable to an experienced layout designer. Helix does not eliminate the designer; instead, it makes him or her dramatically more productive.
To acheive this, an automated solution must handle all three major quality requirements:
- Circuit requirements, such as location, symmetry, matching and guard rings, as defined by an experienced designer
- Device requirements, such as well merging, abutment, interdigitation & row stacking, which are required for minimum-area layout. These are understood by all layout designers, but have historically been difficult for automated tools to implement correctly.
- Process requirements, defined by the process design rules
Ciranova Helix introduces technological advances to assist designers with the Circuit requirements, and automate the Device and Process requirements:
Compact, process-portable constraints capture circuit requirements
Ciranova Helix uses high-level constraints to guide its placement. The format is compact, open and easily understood by circuit and layout designers. Constraints are applied using a point-and-click graphical user interface (GUI); power users may prefer to edit the text file directly.
Some earlier attempts at analog layout automation required the user to input extremely granular constraints, for every device and relationship. In contrast, Helix uses relatively few constraints applied at a much higher level, similar to the guidance a circuit designer gives to a layout designer. The mechanics of device manipulation and process design rule compliance are handled automatically by the tool; the user doesn't need to define them with constraints. To read more about Ciranova Helix constraints and the point-and-click GUI, click here.
Automatic device-level abutting, well merging, interdigitation and row stacking
Ciranova Helix is the first automated analog layout solution that automatically takes advantage of PyCell features such as abutting, well merging, interdigitation and row stacking in order to create more compact layout. By default, Ciranova Helix globally abuts connected devices, merges wells where appropriate, and stacks rows of fingers to achieve denser layout. The user may choose to override these behaviors on any or all devices if desired.
DRC-correct placement using Ciranova RuleWise Technology
Ciranova Helix placements are DRC-correct-by-construction, even at advanced geometries with DFM and other complex design rules. This avoids the need for tedious manual repair of DRC violations in a layout editor, and enables rapid convergence on optimal layouts.
Ciranova's RuleWise technology enables our products to create design-rule-correct geometry without requiring the end-user to provide process-specific input. To read more about RuleWise Technology and the RuleWise engine, click here
Area Efficiency at 65nm and Below
In many cases Helix can actually help the designer improve area efficiency, for two reasons:
First, the traditional layout cycle takes so long that development teams usually have little time for comprehensive floorplan exploration. Instead, they must quickly choose a direction based on estimated block areas, and then proceed directly to bottom-up detailed placement. This time-constrained process may not find the most area efficient design.
Second, the number of design rules at 65nm and below is so large that few designers have time to fully optimize their layout to all of these rules at once. Instead, designers often focus on a few key rules, and simply leave extra area margin in order to accommodate the others and still meet the schedule.
Ciranova Helix overcomes both limitations. It places the entire circuit at once at the device level, ensuring a very accurate picture of how the full design will look in layout; and because Helix run times are so short, designers can explore many floorplan strategies before settling on a preferred one. Ciranova Helix also automatically generates multiple optimized placement footprints at different aspect ratios, giving designers a range of choices.
Ciranova Helix also uses the RuleWise engine to create the fine-grained placement. The RuleWise engine easily handles the full range of design and DFM rules in advanced processes. Essentially the optimization of the layout for design rules is turned over to the computer; the result is layout that takes maximum advantage of the silicon's full potential. Click here to learn more about Ciranova RuleWise Technology.
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