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Ciranova Helix Performance

The performance figures shown below were gathered for designs running on a foundry 65nm process. Ciranova Helix performance varies with CPU, memory, design hierarchy, process technology and applied constraints.


Design Device Count Hierarchy Ciranova Helix
run time
Design #1 1765 55 blocks 2 hr 30 min
Design #2 183 12 blocks 2 min 50 sec
Design #3 22 1 block 15 sec

A User Benchmark

A Ciranova Helix user posted a product review with performance data to the ESNUG user group. Here are his benchmark results for a 40-transistor circuit on a foundry 65nm process:

Number of Constraints Ciranova Helix run time
[unconstrained] 5 min 10 sec
10 constraints 2 min 29 sec
18 constraints 28 sec

Note that performance improves as number of constraints increases. Click here to read the complete review.


Learn More about Ciranova Helix

 

 

 

 

 

 

 

 

 

 

XPyCell
Universal OpenAccess PCells, created using Ciranova's PyCell Studio software. PyCells are authored using the popular Python programming language, hence the name.
XAMS
Analog/Mixed Signal
XPyros Layout Viewer
A component of Ciranova's PyCell Studio software. The Pyros Layout Viewer can open any OpenAccess block, select layout objects for examination, and manipulate PyCell parameters. Pyros also includes a built-in design rule checker that allows users to check the layout interactively.