And now, here's the main content of this page:
Rapid Analog Program: Get to Parasitics Fast
"I love Helix. It's incredibly fast, and it's correct. For fast prototyping there's nothing else like it. I can't imagine going back to the old way."
Senior Serdes Design Engineer, 40/28nm - February, 2010
Do you have an analog or RF circuit that would benefit from getting back parasitics and other layout data in hours or days, instead of weeks? To demonstrate how quickly Ciranova Helix® can be integrated into your layout environment, Ciranova™ has created the Rapid Analog Program. Send us a design, we'll bring it up in Helix, and you can experience the joy of exploring multiple design rule correct layouts for parasitic extraction in just a few hours.
Program Description
It's easy. First, you send us a design. We'll bring it up in Helix. We meet at your office, our office, or via web conference. Together, we'll do more layout in two hours than you've ever done in a week, using your own design.
Step 1: Send us a design.
Here's what to send:
- Netlist (CDL or SPICE format)
- Schematic (PDF, screenshot or library format)
- Reference layout, if you want Helix to match it (GDSII and layer map with descriptions)
- Specify a target process technology (foundry & node)
Step 2: Tell us your goals
Think about your goals, and what you could accomplish if you could get layout back in hours or days. Some ideas to consider:
- Do you want us to replicate your existing layout, so you can compare how long Helix takes?
- Do you want to develop a fast parasitic flow, to get extracted parasitics back to circuit designers within a certain amount of time?
- Do you want to reduce the calendar time required for layout, to cut costs and resource requirements?
- Do you need to respond quickly to circuit, PCell or design rule changes?
- Do you just want to try a lot of different floorplans quickly, in order to find the one you like best?
Step 3: Meet with Ciranova
The best way to do this is face to face, where we can work together on your design. You'll be able to interactively request layout changes, and see how easy they are to implement using Helix. However, if some team members are remote, we can schedule a WebEx conference to do the same thing.
In either case, here are some of the things we can do when we meet:
- Compare your hand-built layout to Helix layout, and compare the time taken for each.
- Explore alternate layouts. Helix creates many design-rule-correct layouts so that you can choose what works best.
- Make interactive changes to your layout, so you can understand the learning curve (low) and the run time (fast)
- Migrate your design to new processes. Using Helix, you can do this very rapidly, typically in minutes.
A couple of hours is usually sufficient. By the end of the meeting, you will know exactly how Helix performs on your design, and what benefits you can expect.
Program Cost
The cost of a Fast Parasitic Program session is $9,000. This cost may be waived if you are targeting a process from a Ciranova foundry partner such as TSMC. Most popular CMOS processes at 65nm and below are already supported, and more processes are added monthly. Use the form below to see if your target process is already available.
How to Get Started
Just contact Ciranova, we'll take care of the rest. Do it today!