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Agile Layout White Paper
The complexity of nanometer CMOS design rules has greatly complicated the task of creating and integrating analog/mixed-signal functions in SoC designs. Traditionally, custom layout is tedious and inflexible once started. As a result, design teams don't start layout until the circuit design is nearly complete, and typically work under strong tapeout pressure. However, a much more agile approach is possible using automated methods, which reduce the total effort needed, enable layout to proceed concurrently with circuit design, and typically produce more optimal layouts, especially, smaller die sizes.
This white paper is intended for circuit and layout designers and design managers involved with high-speed, advanced-node and other layout- and DFM-sensitive custom IC development. Please submit your name and address below to download.