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Top Three Hurdles of AMS Layout Design
At least three major obstacles impede
Design Rule Complexity
As feature sizes continue to shrink, the number and complexity of design rules increases dramatically. Typical 90nm processes require hundreds of rules, and at 65nm the count goes into the thousands. These rules may include:
- Recommended rules to increase yield
- Different rule sets for different process variants
- Conditional rules
A designer creating something as simple as a basic MOS transistor must now take into account dozens of design rules (minimum size, spacing, enclosure, overlap, density, etc.) for each process technology. This problem is compounded when multiple process technologies and variations must be supported.
Re-use
PCell and layout generator designers learned long ago not to hard-code absolute spacing into their code. The most common design practice today is to reference design rules from a technology file to define object spacing. Designers using traditional PCell design techniques must identify and explicitly reference the applicable design rules each time they create and place an object. Using the MOS transistor example above, to create all the geometry on all the layers may require the designer to include explicit references to dozens of design rules. Unfortunately, hard-coding these design rules into the PCell makes it difficult to migrate the PCell and circuits which use it to another process technology.
Portability
Libraries of PCells generally work only with the EDA platforms on which they were developed. PCells written in SKILL®, for instance, work only in the set of tools supplied by Cadence. Thus attempting to transfer design data from one vendor's environment to another can be a major undertaking. Worse still, this process might require PCells to be "flattened," or the whole design streamed out as GDSII, which results in a loss of design flexibility.